This invention relates to insulated-gate field-effect transistors, particularly but not exclusively so-called power "D-MOS" and "V-MOS" transistors suitable for high power and fast switching applications.
Insulated-gate field-effect transistors are known comprising a semiconductor body having a surface-adjoining source region of one conductivity type which is surrounded in the body by a surface-adjoining second region of the opposite conductivity type, the second region being surrounded in the body by a surface-adjoining third region which is of said one conductivity type and is associated with the drain of the transistor. An insulating layer is present on a part of the second region, and a conductive layer is present on said insulating layer to form an insulated gate of the transistor for capactively controlling in said part of the second region a conductive channel between the source region and a first part of the third region. Different specific types of this known transistor structure are described in, for example, I.E.E.E. Transactions on Electron Devices, Vol. ED-25, No. 11 (November 1978), pages 1325 to 1327, and Vol. ED-27, No. 2, (February 1980), pages 340 to 343, and Electronics, Nov. 22, 1979, pages 85 and 86 and Aug. 28, 1980, pages 145 to 147.
The article in I.E.E.E. Transactions ED-25 describes a high voltage double-diffused lateral D-MOS transistor in which the source and second regions are diffused into the third region and in which a drain region is also present and contacted at the same major surface of the body as the source and second regions. This particular D-MOS transistor is also suitable for incorporation in a monolithic integrated circuit. The article in I.E.E.E. Transaction ED-27 describes a high power double-diffused vertical D-MOS transistor in which the source and second regions are diffused into the third region (an epitaxial layer) and in which a drain region is provided by the substrate and contacted at the opposite major surface of the body from the source and second regions. The 1979 article in Electronics describes power V-MOS transistors which have a vertical source-drain configuration and a groove extending through the double-diffused source and second regions, the insulated gate being present on the walls of the groove. The 1980 article in Electronics describes a high power vertical transistor of the D-MOS type in which the source and second regions are formed by a double implantation instead of double diffusion. Non-power low voltage types of said known transistor structure are also fabricated in integrated circuits, especially in a lateral D-MOS configuration. In this case, the bulk of the semiconductor body may form the third region of a plurality of such transitors.
These insulated-gate field-effect transistors can have a high switching speed. This high speed is assisted by the fact that they are unipolar majority carrier devices. Thus minority charge carriers are not involved in current transport through the transistor so that the turn-off rate of the transistor is not reduced by minority carrier storage effects such as occur in the base regions of bipolar transistors. However the Applicants have found that, particularly when used to drive inductive loads, the turn-off of such an insulated-gate field-effect transistor is slower than expected. The Applicants believe that this reduction in speed results from the p-n junction between the second and third regions being temporarily forward-biased by the overswing voltage from the inductive load as a result of which minority charge carriers can be injected into the third region from the second region and cause minority carrier storage effects. Furthermore the Applicants consider that using a forward-biased junction of such a transistor to clamp the voltage overswing can be desirable to avoid exceeding the breakdown voltage of the transistor and to recover the inductive energy and return it to the power supply.